Training Workshop:
Verilog and SystemVerilog Language Primer
Overview
The Verilog and SystemVerilog Language Primer is a fast-paced workshop designed to help engineers read, understand, and maintain digital hardware models and conventional verification testbenches written in Verilog and SystemVerilog. Critical language foundations are presented, including the proper use of data types, 2-state versus 4-state modeling, enumerated types, structures, and SystemVerilog's versatile set of programming statements. Hands-on labs reinforce the concepts discussed during the class lectures.
Critical language foundation! This workshop provides an essential foundation for more advanced training on SystemVerilog, including writing object-oriented and constrained random verification testbenches, and coding SystemVerilog Assertions.
Not just for beginners! Engineers who have years of experience with Verilog often comment regarding how much they learn and benefit from the details provided in this workshop.
Available Formats and Course Lengths
• Instructor-led onsite private workshop: 2-days
• Instructor-led eTutored™ live online workshop: 2-days
• Instructor-mentored eTutored™ self-paced online workshop: 2 to 30 days
Intended Audience and Objectives
This workshop is ideal -- and important -- for three primary groups:
- Engineers and managers who need to read and understand Verilog/SystemVerilog hardware models or verification testbenches, but who will not be writing large amounts of code.
- Engineers who will be attending advanced training on verification. The knowledge gained in this workshop provides the prerequisite foundation for Sutherland HDL's "SystemVerilog Object Oriented Verification" and "SystemVerilog Assertions for Design Engineers and Verification Engineers" workshops.
- Long-time users of Verilog who need to understand the important enhancements SystemVerilog has added to traditional Verilog, and why those enhancements are important to use.
(The information presented in this workshop can be combined with other workshops, and is integrated into Sutherland HDL's "Verilog/SystemVerilog for Design and Synthesis" workshop.)
Prerequisite Knowledge
Attendees should be familiar with general digital hardware engineering concepts such as the difference between combinational logic and sequential logic, binary and hexadecimal number systems, and binary operations.
Included Materials
- Full-color training binder with lecture slides, lab instructions, and supplemental information. (eTutored™ self-paced courses receive an eBook instead of a binder.)
- A handy "Verilog HDL Quick Reference Guide" booklet.
- Lab files, including example solutions that illustrate proper and efficient coding styles.
Customized Training
At times, your engineering team may require unique training to meet the needs of your specific projects. Sutherland HDL can customize our standard workshops to meet those needs, when presented as a private onsite or online workshop. request info
