SystemVerilog Synthesis for Verilog Design Engineers

Workshop Highlights

• 2-day in-depth workshop, with 60% lecture and 40% lab
• Detailed coverage of the synthesizable subset of the IEEE 1800-2005 SystemVerilog standard
• How to best use new data types, structures, interfaces, basic assertions, etc.
• Emphasis on advanced-level modeling for simulation and synthesis

Overview

SystemVerilog Synthesis for Verilog Design Engineers is a 2-day intensive workshop covering the hardware modeling portions of the new IEEE 1800-2005 SystemVerilog standard. SystemVerilog is an exciting and powerful set of extensions to the Verilog Hardware Description Language, that enable efficiently modeling and verifying large, complex designs. The synthesizable subset of SystemVerilog presented in this workshop allows engineers to model more functionality with fewer lines of code, and at the same time ensure that models synthesize correctly and optimally. Simply put, SystemVerilog makes the design engineers life much easier and enables greater design productivity. This workshop is not a simple (and boring) language course. The focus of this workshop is on the proper usage of the extensive set of advanced modeling capabilities offered by SystemVerilog. Several labs reinforce the principles presented, with forty percent of the class time devoted to hands-on experience.

A comprehensive student guide, a handy "Verilog HDL Quick Reference Guide" ($15 value), and the book "SystemVerilog for Design" by Sutherland, Davidmann and Flake ($125 value) are included with the course materials.

For an overview of the SystemVerilog standard, refer to "An Overview of SystemVerilog 3.1" a white paper reprint of an EE Design article by Stuart Sutherland.

Workshop Objective

This workshop will enable design engineers who use Verilog to immediately be productive modeling complex hardware designs using the SystemVerilog extensions to the Verilog language.

Intended Audience

This workshop is for experienced Verilog design engineers. The course presupposes a working knowledge of Verilog, and only covers the SystemVerilog enhancements to Verilog. Design engineers who do not have a strong background in Verilog should take Sutherland HDL's "Comprehensive Verilog-2005 with SystemVerilog Synthesis Extensions" workshop.

Related Workshops

• Accelerated Verilog-2005 with SystemVerilog Synthesis Extensions
• Comprehensive Verilog-2005 with SystemVerilog Synthesis Extensions
• SystemVerilog Testbench for Verification Engineers
• SystemVerilog Assertions for Design and Verification Engineers

Prerequisites (essential)

SystemVerilog is a major set of extensions to the Verilog language. Knowledge of the Verilog HDL is mandatory! Without this prerequisite knowledge, students cannot fully benefit from this workshop.

Comments

"SystemVerilog represents the most significant advancement to the Verilog language, since its acceptance as an IEEE standard. It takes Verilog to the next abstraction level--the architecture and behavioral design of a system--and adds to it powerful assertions that allow designers and system architects to build and verify full systems."

Dennis Brophy, Accellera Chairman

"Advances in technology and growing design complexity have made it necessary to move HDLs to the next level to support system design. As a founding member of Accellera, we are pleased to be part of this effort with other users and EDA tool suppliers and encourage design, verification engineers to adopt and deploy SystemVerilog."

Shrenik Mehta, Sr. Engineering Manager, Global Testability, Tools and Validation, Sun Microsystems

Syllabus

Click here to download the full syllabus for all Sutherland HDL workshops (a PDF document).

Workshop Locations

This workshop can be presented on-site, at your facilities. We also offer several public workshops throughout the year, in locations such as San Jose, California; Portland, Oregon; Austin, Texas and Boston, Massachusetts.