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"The best class I have ever taken! The lecture was thorough. The labs were fun and critical to understanding the concepts."

Public Workshop Schedule

Early Registration Discount: Register at least 4 weeks before a workshop date, and the cost will automatically be reduced by 5%!

May 2008
19-20	SystemVerilog Synthesis Extensions for Verilog Design Engineers (2-days) Phoenix, Arizona [location details] Includes the book "SystemVerilog for Design" ($125 value) Register	$1,250
21-23	Combined SystemVerilog Testbench and SystemVerilog Assertions (3-days) Phoenix, Arizona [location details] Includes the books "SystemVerilog for Verification" ($125 value) and "SystemVerilog Assertions Handbook" ($150 value) Register	$1,800

Our open-enrollment schedule for summer and fall of 2008 has not yet been finalized.
Contact Us us for workshop schedule plans beyond these dates, or to request a specific workshop and location.
You can also register to receive updates to our open-enrollment schedule by e-mail.

Sutherland HDL can also present on-site workshops at your company!
Workshop Pricing and Terms

Public Workshop Schedule

May 2008