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"The best class I have ever taken! The lecture was thorough. The labs were fun and critical to understanding the concepts."

Public Workshop Registration

To register by FAX, download a registration form (PDF format).

To register by online, complete the registration information, below. Sutherland HDL will contact you by phone within 72 hours (3 days) after you submit this form to obtain payment information. Payment can by made by major credit card, or by company check. A seat in a workshop is not guaranteed until payment information is received.

Please call us at +1-503-692-0898 if you have any questions regarding workshop registration.

Early Registration Discount: Price will automatically be reduced by 5% when registering at least 4 weeks before a workshop date!

Select the workshop for which you wish to register

May 19-20, 2008: SystemVerilog Synthesis for Verilog Design Engineers, Phoenix, Arizona, $1,250

May 21-22, 2008: SystemVerilog Testbench for Verilog Verification Engineers (1-1/2 days), Phoenix, Arizona, $1,250

May 22-23, 2008: SystemVerilog Assertions for Design and Verification Engineers (1-1/2 days), Phoenix, Arizona, $1,250

May 21-23, 2008: combined SystemVerilog Testbench and SystemVerilog Assertions (3-days), Phoenix, Arizona, $1,800

May 21-23, 2008: combined SystemVerilog Synthesis, Testbench and Assertions (5 days), Phoenix, Arizona, $2,750

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Terms and Conditions:
Cancellations prior to 2 weeks before the workshop will receive a full refund of the tuition. Cancellations within 2 weeks of the workshop will receive a 50% refund of the tuition. Cancellations after the workshop has started, or no-show students, are not eligible for a refund. Sutherland HDL reserves the right to reschedule or cancel an open-enrollment workshop 2 weeks prior to the start date if there is insufficient enrollment. 100% of the tuition will be refunded if a workshop is canceled, or if you do not wish to attend a rescheduled workshop. Credit card payments are not charged until 2 days before the workshop start date.
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