Workshop Descriptions

eTutored™ live Online Workshops

Sutherland HDL eTutored™ live online workshops are instructor-led workshops that provide all the same learning benefits as classroom based training, but with greater flexibility to mix expert training and work responsibilities.

Details

eTutored™ self-paced Online Workshops (anticipated availablity Q4-2013)

Instructor-assisted comprehensive training anytime and anywhere -- the utmost in schedule flexibility. Sutherland HDL eTutored™ self-paced online courses provide one-on-one tutoring from experienced SystemVerilog experts.

Details

Verilog/SystemVerilog for Design and Synthesis

• 4-day comprehensive training on the latest generation of the Verilog/SystemVerilog language
• Mastering Verilog and SystemVerilog's programming language and best practices
• Modeling complex designs using the synthesizable subset of Verilog and SystemVerilog
• Audience: This workshop is for digital engineers who will be designing ASICs, FPGAs or systems with Verilog.

Description & Syllabus (PDF)
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SystemVerilog Object-Oriented Verification

• 4-day advanced-level workshop on using SystemVerilog for verification
• Mastering Verilog and SystemVerilog's programming language and best practices
• Writing object-oriented testbenches using inheritance and polymorhphism
• Using semaphores, mailboxes, dynamic arrays, constrained random testing, and coverage
• Audience: This workshop is for design and verification engineers who will be verifying digital designs

Description & Syllabus (PDF)
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Mastering SystemVerilog UVM (Universal Verification Methodology)

• 3-day workshop on developing testbenches using the UVM verification standard
• Using SystemVerilog with a consistent verification methodology
• Writing UVM testbench components following best-practices coding styles
• Devoloping highly configurable and reusable verifcation environments
• Audience: This workshop is for verification engineers who are already familiar with the SystemVerilog verification constructs

Description & Syllabus (PDF)
eTutored™ Workshop Schedule
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Advanced SystemVerilog Assertions for Design and Verification Engineers

• 2-day advanced-level workshop writing SystemVerilog Assertions
• Writing complex assertion sequences for a variety of complex digital logic circuits
• Undertanding and correctly using the many complex SVA operators
• Audience: Both design engineers and verification engineers will find this course beneficial

Description & Syllabus (PDF)
eTutored™ Workshop Schedule
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Additional Workshops and Services

Sutherland HDL can also provide:

• A 2-day Verilog/SystemVerilog Foundations workshop for engineers that need to read and maintain existing code
• Customized training by combining material from multiple workshops into a single workshop
• Customized training with additional topics developed for specific engineering team needs
• Licensed training materials
• SystemVerilog related course development services
• SystemVerilog design or verification consulting services

Contact Sutherland HDL to discuss custom workshops