Accelerated Verilog-2005 with SystemVerilog Synthesis Extensions

Workshop Highlights

• 2-day workshop, with 75% lecture and 25% lab
• Thorough introduction of the Verilog language, with a focus on reading and verifying models
• Simulation tools used during labs

Overview

Accelerated Verilog-2005 with SystemVerilog Synthesis Extensions is a 2-day accelerated workshop on the IEEE 1364-2005 Verilog Hardware Description Language along with the synthesizable subset of the IEEE 1800-2005 SystemVerilog extensions to Verilog. A practical overview of the language is presented, with a focus on how Verilog is used for modeling hardware and for design verification using digital logic simulation. The workshop materials include a complete student guide and a useful "Verilog HDL Quick Reference Guide". Several labs reinforce the principles presented, with about 25% of the class time devoted to lab work. This accelerated workshop teaches how to read and understand Verilog and SystemVerilog models, and how to model testbenches using the Verilog language. Students learn the keywords, syntax and semantics of Verilog, and how to write small hardware models, how to read and understand more complex models, and how to write testbenches using Verilog. NOTE: Design engineers who need to write synthesizable models should attend the full Comprehensive Verilog with SystemVerilog Synthesis Extensions workshop, which places more emphasis on synthesis rules and has more involved labs.

Workshop Objective

At the conclusion of this workshop, students will be able to read and understand Verilog code, and be able to write and small digital hardware models and testbenches. Students will know proper modeling styles and recognize subtle modeling style errors that can lead to simulation race conditions and poor synthesis results.

Intended Audience

Accelerated Verilog-2005 with SystemVerilog Synthesis Extensions workshop is intended for new Verilog users, engineering managers, technical writers and others who wish to understand how Verilog is used in today's design flows. This accelerated workshop is not a replacement for--or a prerequisite for--Sutherland HDL's 4-day Comprehensive Verilog-2005 with SystemVerilog Synthesis Extensions workshop. Engineers who will be creating Verilog models of complex hardware should attend the comprehensive 4-day Verilog workshop instead of this accelerated workshop.

Related Workshops

• Comprehensive Verilog-2005 with SystemVerilog Synthesis Extensions
• SystemVerilog Synthesis for Verilog Design Engineers
• SystemVerilog Testbench for Verification Engineers
• SystemVerilog Assertions for Design and Verification Engineers

Software Tools Used

Students will use Verilog simulators for labs, such as the Cadence NC-Verilog™, Synopsys VCS™, or Mentor ModelSim™.

Prerequisites (essential)

Knowledge of digital design engineering is required. Without this prerequisite knowledge, students cannot fully benefit from this workshop. Students will be writing Verilog models of basic digital circuits such as shift registers and a small arithmetic logic unit.

Student Comments

"I would strongly recommend this course to anyone that wants to learn more about Verilog, simulation, and modern design practices."

"An excellent class. I had obtained my knowledge of Verilog 'on the job'. I was able to find many misunderstandings about Verilog usage, syntax, etc."

Syllabus

Click here to download the full syllabus for all Sutherland HDL workshops (a PDF document).

Workshop Locations

This workshop can be presented on-site, at your facilities. We also offer several public workshops throughout the year, in locations such as San Jose, California; Portland, Oregon; Austin, Texas and Boston, Massachusetts.