Stuart Sutherland, of Sutherland HDL, Inc.

Mr. Stuart Sutherland is the founder and a principal engineer of Sutherland HDL, Inc., located in Portland Oregon.  Sutherland HDL provides expert Verilog, SystemVerilog, UVM, SVA, and PLI/VPI/DPI training and consulting services.

Mr. Stuart Sutherland is the founder and President of Sutherland HDL, Inc. Stuart is a design engineer and SystemVerilog expert. He holds a BS in Computer Science, with an emphasis in Electronic Engineering and a Masters degree in Education with an emphasis on eLearning online course development. Stuart has been using and teaching Verilog and SystemVErilog since 1988, and has been involved with the Verilog and SystemVerilog standards efforts since their beginnings. He is a member of the IEEE 1800 SystemVerilog standards committee, and is the technical editor of the SystemVerilog Language Reference Manual (LRM). He was also one of the editors of the IEEE 1364-1995, 2001 and 2005 Verilog Language Reference Manuals. Stuart founded Sutherland HDL, Inc. in 1992, over 20 years ago. His company specializes in providing expert training on Verilog, SystemVerilog, UVM and SystemVerilog Assertions.

Mr. Sutherland is the author or co-author of many books and papers on Verilog and SystemVerilog.

A few highlights of Mr. Sutherland's career include:

• Developer of comprehensive training courses on Verilog, SystemVerilog, UVM and the Verilog PLI
• Member of the IEEE 1364 Verilog standards group since its inception in 1993
• Member of the IEEE 1800 SystemVerilog standards group since its inception in 2001
• Chair the PLI task force within the IEEE 1364 standards group
• Editor of the IEEE Verilog 1364-1995, 2001 and 2005 standards
• Editor of the IEEE Verilog 1800-2005, 2009 and 2012 standards
• Program chair of the international Design and Verification Conference (DVCon)
• Author of several books on Verilog and SystemVerilog
• Author of numerous papers on Verilog and SystemVerilog
• Received several "Best Paper" awards at technical conferences