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About Stuart Sutherland

Explanation of Verilog, SystemVerilog and VHDL

Verilog and SystemVerilog Quiz and Tips

Workshop Descriptions

• Comprehensive Verilog and SystemVerilog for Design and Synthesis
• SystemVerilog Synthesis for Verilog Design Engineers
• Accelerated Verilog Primer
• SystemVerilog Testbench for Verilog Verification Engineers
• SystemVerilog Testbench for non-Verilog Verification Engineers
• Advanced SystemVerilog Assertions for Design and Verification Engineers
• Advanced SystemVerilog Open Verification Methodology (OVM)
• Practical Application of the Verification Methodology Manual using SystemVerilog (VVM)
• Verilog-2005 PLI 2.0 (VPI) with SystemVerilog DPI
• Comprehensive VHDL for Synthesis and Verification

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Books by Stuart Sutherland

• SystemVerilog For Design
• SystemVerilog for Verification
• Verilog and SystemVerilog Gotchas
• Verilog-2001
• The Verilog PLI Handbook
• Verilog HDL Quick Reference Guide
• Verilog PLI Quick Reference Guide

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