Papers by Stuart Sutherland

2013

• SNUG Silicon Valley Synopsys Users Group Conference (Awarded Best Presentation, First Place):
  Synthesizing SystemVerilog: Busting the Myth that SystemVerilog is only for Verification (co-authored with Don Mills)
  paper | presentation slides
• DVCon Conference, San Jose, California:
  I'm Still In Love With My X (advantages and hazards of X propagation in simulation)
  paper | presentation slides

2012

• Design Automation Conference (DAC), San Francisco, California:
  Summary of What is New in SystemVerilog-2012
  presentation slides
• DesignCon Conference, Santa Clara, California:
  What, If Anything, In SystemVerilog Will Help Me With FPGA-based Design?
  paper | presentation slides
• DVCon Conference, San Jose, California:
  What's New in SystemVerilog-2012
  paper | presentation slides

2009

• Design Automation Conference (DAC):
  SystemVerilog Is Getting Even Better! An Update on the Proposed SystemVerilog-2009 Standard
  a joint presentation by Cliff Cummings of Sunburst Design and Stuart Sutherland of Sutherland HDL)
  presentation, Part 1 by Sunburst Design
  presentation, Part 2 by Sutherland HDL
• SNUG San Jose Synopsys Users Group Conference:
  Is SystemVerilog Useful for FPGA Design? (" Burn-and-Learn" versus " Learn-and-Burn")
  paper | presentation slides
• DVCon Conference, San Jose, California:
  Adding Last-Minute Assertions: Lessons Learned (a little late) about Designing for Verification
  paper | presentation slides

2008

• DVCon Conference, San Jose, California:
  Verilog Is Not Called Verilog Anymore! The Merging of the Verilog and SystemVerilog IEEE Standards
  paper | presentation slides
• Cypress Logic Excellence Summit, San Jose
  Push Button Engineering and Top Ten Reasons Engineers Use SystemVerilog
  presentation slides

2007

• SNUG San Jose Synopsys Users Group Conference (Awarded Best Paper):
  More Standard Gotchas: Subtleties in Verilog and SystemVerilog That Every Engineer Should Know (co-authored with Don Mills)
  paper | presentation slides

2006

• SNUG Boston Synopsys Users Group Conference (Awarded Best Technical Paper):
  Standard Gotchas: Subtleties in Verilog and SystemVerilog That Every Engineer Should Know (co-authored with Don Mills)
  paper | presentation slides
• SNUG Europe Synopsys Users Group Conference (Awarded Best Paper):
  Modeling with SystemVerilog in a Synopsys Synthesis Design Flow
  paper | presentation slides
• SNUG San Jose Synopsys Users Group Conference (Awarded Best Paper, 2nd Place):
  SystemVerilog Assertions Are For Design Engineers, Too!
  paper | presentation slides
• DVCon Conference, San Jose, California:
  A Proposal for a Standard Synthesizable SystemVerilog Subset
  paper | presentation slides
• DesignCon Conference, Santa Clara, California:
  Getting Started with SystemVerilog Assertions
  presentation slides

2005

• SNUG San Jose Synopsys Users Group Conference:
  SystemVerilog Saves the Day--the Evil Twins are Defeated! unique and priority are the new Heroes
  paper | presentation slides
• DVCon Conference, San Jose, California:
  SystemVerilog Interoperability Checklist
  paper | presentation slides

2004

• SNUG Boston Synopsys Users Group Conference:
  Modeling FIFO Communication Channels Using SystemVerilog Interfaces
  paper | presentation slides
• DAC Design Automation Conference:
  SystemVerilog Adoption Plan
  presentation slides
• SNUG Europe Synopsys Users Group Conference (Awarded Best Paper):
  Integrating SystemC Models Into Verilog Using the SystemVerilog DPI
  paper | presentation slides
• SNUG San Jose Synopsys Users Group Conference (Awarded Best Technical Paper):
  The Verilog PLI is Dead (maybe) -- Long Live the the SystemVerilog DPI!
  paper | presentation slides
• Mentor User-2-User Conference:
  SystemVerilog, ModelSim and You
  paper | presentation slides
• White paper: SystemVerilog is for Everyone (not just system designers)
  paper |

2003

• EEdesign White paper reprint of magazine article:
  Overview of SystemVerilog 3.1
  paper
• DVCon Design and Verification Conference:
  SystemVerilog 3.1: It's What the DAVEs In Your Company Asked For
  paper | presentation slides
• SNUG San Jose Synopsys Users Group Conference:
  HDVL += (HDL & HVL) SystemVerilog 3.1: The Hardware Description AND Verification Language (co-authored with Don Mills)
  paper | presentation slides

2002

• HDLCon International HDL Conference:
  Verilog, The Next Generation: Accellera's SystemVerilog
  paper | presentation slides
• SNUG San Jose Synopsys Users Group Conference:
  Using PLI 2.0 (VPI) with VCS
  paper | presentation slides
• DesignCon Electronic Design Conference:
  Using Verilog-2001 for Design Verification
  presentation slides

2001

• Wescon Electronic Engineering Conference:
  Using Verilog-2001 for Modeling Hardware
  presentation slides
• Synopsys Users Group Conference:
  Getting the most from Verilog-2001 (co-authored with Don Mills)
  paper | presentation slides

2000

• International HDL Conference:
  What's New in the IEEE 1364 Verilog-2001 Standard
  paper | presentation slides

1999

• Design Automation Conference:
  IEEE 1364 Verilog PLI Standards Group Report
  presentation slides

1998

• International HDL Conference:
  IEEE 1364 Verilog PLI Standards Group Report
  presentation slides
• International HDL Conference:
  Using the PLI VPI Library
  paper | presentation slides

1997

• International HDL Conference:
  IEEE 1364 Verilog PLI Standards Group Report
  presentation slides
• Cadence Users Group Conference:
  Switching to the New PLI Standard
  presentation slides
• Cadence Users Group Conference:
  Will Cadence Miss the Boat?
  presentation slides

1996

• Cadence Users Group Conference:
  Understanding Nonblocking Assignments
  presentation slides

1995

• International Verilog Conference (Awarded Best Paper):
  The IEEE 1364-1995 Verilog PLI Standard
  presentation slides

1994

• International Verilog Conference:
  Modeling for best simulation performance
  tutorial slides