Books by Stuart Sutherland
Stuart Sutherland, founder and President of Sutherland HDL, Inc., has authored or co-authored several books on Verilog and SystemVerilog. These books are described below, along with information on obtaining the code examples from these books.
Other places to order these and other Verilog and SystemVerilog books:
SystemVerilog is a rich set of enhancements to the IEEE 1364 Verilog-2005 Hardware Description Language. These extensions address two major issues of HDL based design: modeling complex designs for synthesis, and writing high-level test programs to efficiently verify these large designs. This book addresses the first purpose of SystemVerilog, modeling large designs. The focus of the book is how to properly use the SystemVerilog extensions to Verilog to write models that both simulate and synthesize correctly. This second edition reflects the official IEEE 1800-2005 SystemVerilog standard. This book assumes that the reader is already familiar with using Verilog, and needs to learn the synthesizable extensions that SystemVerilog adds to Verilog. The SystemVerilog extensions described in this book include:
• Packages and the $unit declaration space
• Modeling with new 2-state data types
• Representing complex data with structures, unions and arrays
• Using user-defined data types and enumerated data types
• Proper usage of new synthesizable procedural blocks
• Working with enhanced procedural programming statements and operators
• Simplifying design hierarchy using interfaces and new netlist shortcuts
• Using SystemVerilog for abstract, transaction level modeling
Sorry, but the second edition examples are not available for download (we just have not had time to properly document and package all of the example files). Register to receive an e-mail notification when the examples become available.
Download the first edition examples (UNIX tar file) and first edition errata (text file).
This is the companion to to the SystemVerilog for Design book. This book covers the many significant testbench extensions that SystemVerilog adds to Verilog. Refer to the author's web page for a full description of this book.
This book has a mistake on almost every page! On purpose. The book shows common coding mistakes that the authors or others have made in their Verilog or SystemVerilog code. Often these mistakes looked like perfectly reasonable code, but cause functional errors in simulation or synthesis that were difficult to debug. And that's the definition of a Gotcha -- code that looks correct, but which behaves differently than expected.
Sorry, but the examples in this book are not available for download (we just have not had time to properly document and package all of the example files). Register to receive an e-mail notification when the examples become available.
The IEEE 1364-2001 standard, nicknamed "Verilog-2001", is the first major update to the Verilog language since its inception in 1984. This book presents 45 significant enhancements contained in Verilog-2001 standard. A few of the new features described in this book are:
• ANSI C style port declarations for modules, primitives, tasks and functions
• Automatic tasks and functions (re-entrant tasks and recursive functions)
• Multidimensional arrays of any data type, plus array bit and part selects
• Signed arithmetic extensions, including signed data types and sign casting
• Enhanced file I/O capabilities, such as $fscanf, $fread and much more
• Enhanced deep submicron timing accuracy and glitch detection
• Generate blocks for creating multiple instances of modules and procedures
• Configurations for true source file management within the Verilog language
This book assumes that the reader is already familiar with using Verilog. It supplements other excellent books on how to use the Verilog language.
The Verilog PLI provides a means to customize a Verilog simulator to perform virtually any engineering task desired, such as adding custom design debug utilities to a simulator, adding proprietary file read/write utilities to a simulator, interfacing C language models to a simulator, etc. The PLI Handbook serves as both a user's guide for learning how to use the Verilog PLI, and as a comprehensive reference manual on the Verilog PLI standard. There are two major generations of the Verilog PLI: the TF/ACC generation (sometimes called "PLI 1.0") and the VPI generation (sometimes called "PLI 2.0"). Both generations are included in the IEEE 1364 Verilog standard. The older TF/ACC generation has been used in thousands of PLI applications and is portable to nearly all Verilog simulators. The VPI generation offers much more capability and power, and is recognized as the future direction of the Verilog PLI. This book provides equal and detailed coverage of both the TF/ACC and the VPI generations of the PLI.
"This book brings clarity to the Verilog Programming Language Interface. The descriptions and examples shed new light on aspects of the PLI that had previously been murky. Stuart Sutherland has produced the definitive guide to all versions of the PLI. I highly recommend this book to all Verilog users who want to learn the PLI." Chris Spear, Verification Consultant, Synopsys, Inc.
Download PLI book examples (UNIX tar file)
For additional examples, see Chris Spear's PLI Web Page, and David Robert's PLI socket communications example (UNIX tar file).