Home Workshop Descriptions eTutored™ Online Schedule Request Training Workshop Pricing & Terms Books by Stuart Sutherland Papers by Stuart Sutherland Online Reference Guides Links to Other Sites Contact Us

"The best class I have ever taken! The lecture was thorough. The labs were fun and critical to understanding the concepts."

Welcome

Sutherland HDL provides expert training workshops on Verilog and SystemVerilog.

Sutherland HDL training workshops help engineers become true Verilog and SystemVerilog wizards! Workshops are developed and presented by engineering experts with many years of experience in design and verification. Sutherland HDL has trained thousands of engineers throughout the United States, and in Canada, England, Germany, Japan, Malaysia, and Hong Kong.

Sutherland HDL's expert training workshops are now available online!

Sutherland HDL's eTutored™ live online workshops are instructor-led workshops that provide all the same learning benefits as classroom based training, but with greater flexibility to mix training and work responsibilities.

eTutored™ live workshops can be scheduled for a time that best meets your company's training needs, with a low minimum class size of just four engineers (request training).
Sutherland HDL also holds perioding public eTutored™ live workshops (check current schedule).

More...

Training Workshops

SystemVerilog for Design and Synthesis
detailed description (PDF)

SystemVerilog Verification Foundations
detailed description (PDF)

Mastering UVM (Universal Verification Methodology)
detailed description (PDF)

SystemVerilog Assertions for Design and Verification Engineers
detailed description (PDF)

Stuart Sutherland, founder of Sutherland HDL, is a recognized Verilog and SystemVerilog expert, with more than 23 years of experience with Verilog and SystemVerilog. He is an active member of the IEEE Verilog and SystemVerilog standards group. He is also been a technical editor for every version of the IEEE Verilog and SystemVerilog Language Reference Manuals since the standards began. Mr. Sutherland has authored several popular books and conference papers on Verilog and SystemVerilog.

Stuart Sutherland holds a Bachelors Degree in Computer Science with an emphasis in Electronic Engineering Technology and a Masters Degree in Education with an emphasis on eLearning online course development.

Verilog and SystemVerilog Quiz and Tips

Why does this incrementor model work sometimes, and but not all of the time? For example, when the "in" input value is 5, the output value is 6; but when "in" is -5", the output is 252.

module incrementer_with_overflow ( input logic clock, resetN, input logic signed [7:0] in, output logic signed [8:0] out ); always @(posedge clock or negedge resetN) if (!resetN) out <= 0; else out <= in + 1'b1; endmodule

How does adding 1 to -5 end up as 252?

See the answer

Coding Tips Sign-Up

Name Email