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Open-Enrollment Workshops

Verilog/SystemVerilog for Design and Synthesis

September 14-18, 2015

5-days, $2,000 USD per person

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SystemVerilog Object Oriented Verification

October 5-9, 2015

5-days, $2,000 USD per person

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Mastering SystemVerilog UVM

October 20-23, 2015

4-days, $1,500 USD per person

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SystemVerilog Assertions for Design Engineers and Verification Engineers

November 3-5, 2015

3-days, $1,000 USD per person

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Sutherland HDL provides expert Verilog and SystemVerilog training services that help engineers become true Verilog and SystemVerilog wizards!

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