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Open-Enrollment Workshops

Verilog/SystemVerilog for Design and Synthesis

October 2-6, 2017

5-days, $2,000 USD per person

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SystemVerilog Object Oriented Verification

September 11-15, 2017

5-days, $2,000 USD per person

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Mastering SystemVerilog UVM

September 18-21, 2017

4-days, $1,500 USD per person

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SystemVerilog Assertions for Design Engineers and Verification Engineers

October 9-11, 2017

3-days, $1,000 USD per person

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"RTL Modeling with SystemVerilog
for Simulation and Synthesis"




Sutherland HDL provides SystemVerilog training services

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