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"The best class I have ever taken! The lecture was thorough. The labs were fun and critical to understanding the concepts."

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Sutherland HDL provides expert training workshops on Verilog and SystemVerilog. We periodically hold open enrollment public workshops at various locations across the nation. For your convenience, you may also request that we present our workshops on-site at your company.

Sutherland HDL training workshops help engineers become true Verilog and SystemVerilog wizards! Workshops are developed and presented by engineering experts with many years of experience in design and verification. Our design-oriented workshops emphasize creating models that use logic synthesis correctly and avoiding coding gotchas. Verification-oriented workshops emphasize writing assertion-based, constrained random, object-oriented testbenches. Sutherland HDL has trained thousands of engineers throughout the United States, and in Canada, England, Germany, Japan, Malaysia, and Hong Kong.

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Comprehensive Verilog-2005 with SystemVerilog Synthesis Extensions
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SystemVerilog Synthesis for Verilog Design Engineers
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SystemVerilog Testbench for Verification Engineers
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SystemVerilog Assertions for Design and Verification
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Stuart Sutherland, founder of Sutherland HDL, is a recognized Verilog and SystemVerilog expert, with more than 20 years of experience with Verilog and SystemVerilog. He is a member of the IEEE 1364 Verilog standards group and IEEE 1800 SystemVerilog standards group. He is also the editor of the Verilog and SystemVerilog Language Reference Manuals. Mr. Sutherland has authored several popular books and conference papers on Verilog and SystemVerilog.

Verilog and SystemVerilog Quiz and Tips

The example below models a flip-flop with asynchronous set/reset logic (active low). The model synthesizes correctly, but there is a corner case where simulation results are incorrect. What is the corner case?

always_ff @(   posedge clk
            or negedge rst_n     // active-low reset
            or negedge set_n     // active-low set
           )
  if (!rst_n)           // reset has priority over set
    q_out <= ’0;        // reset all bits to zero
  else if (!set_n)
    q_out <= ’1;        // set all bits to one
  else
    q_out <= data_in;   // d input assignment

See the answer

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