Sutherland Logo Graphic Motto Graphic
Home Workshop Descriptions eTutored™ Online Schedule Register for a Workshop Request Private Training Workshop Pricing & Terms Books by Stuart Sutherland Papers by Stuart Sutherland Online Reference Guides

"The best class I have ever taken! The lecture was thorough. The labs were fun and critical to understanding the concepts."


Sutherland HDL provides expert Verilog and SystemVerilog training services.




Sutherland HDL's expert training materials are now available for internal training!

Sutherland HDL training workshops help engineers become true Verilog and SystemVerilog wizards! Workshops are developed and presented by engineering experts with many years of experience in design and verification. Sutherland HDL has trained thousands of engineers throughout the United States, and in Canada, England, Germany, Japan, Malaysia, and Hong Kong.

Sutherland HDL's best-in-class training services are available as:

  • Onsite classroom workshops conducted when and where your needs training (request training)
  • eTutoredlive online public workshops (open-enrollment) (check current schedule)
  • eTutoredlive online private workshops (just your company) (request training)
  • eTutoredself-paced online workshops tutored by engineering experts (available Q4-2014)
  • Licensed training materials for use in internal training programs, with train-the-trainer service (call +1-503-692-0898 to discuss)

Sutherland HDL's eTutoredlive online workshops are instructor-led workshops that provide all the same learning benefits as classroom based training, but with greater flexibility to mix training and work responsibilities.  eTutoredlive private workshops can be scheduled for a time that best meets your company's training needs, with a low minimum class size of just four engineers.  eTutoredlive public workshops are ideal new-hires, interns or when when you need training for one to three engineers.  More details...


Training Workshops



Stuart Sutherland, founder of Sutherland HDL, is a recognized Verilog and SystemVerilog expert, with more than 23 years of experience with Verilog and SystemVerilog. He is an active member of the IEEE Verilog and SystemVerilog standards group. He is also been a technical editor for every version of the IEEE Verilog and SystemVerilog Language Reference Manuals since the standards began. Mr. Sutherland has authored several popular books and conference papers on Verilog and SystemVerilog.

Stuart Sutherland holds a Bachelors Degree in Computer Science with an emphasis in Electronic Engineering Technology and a Masters Degree in Education with an emphasis on eLearning online course development.


Verilog and SystemVerilog Quiz and Tips

This quiz shows a subtle "gotcha" with SystemVerilog Assertions.  The example comes from a real problem encountered at a commpany, though the code has been simplified to focus on the "gotcha" in the assertion.

The assertion verifies that the value of a parity bit is set correctly for the value of data for every clock cycle.  An assertion failure indicates something is wrong with either data or the parity generator logic. 

Assertion Code

property p_parity_check;
  @(posedge clk)
  disable iff (!rstN)  // no checking during active-low reset
  parity == ^data;

pcheck: assert property (p_parity_check)
else $error("PARITY ERROR at %0d ns: data = %h, even parity = %b (expected %b)\n",
            $realtime, data, parity, ^data);

This assertion has a subtle "gotcha" when there is an assertion failure.  To illustrate the problem, the design under test for this example always generates a 1 for the parity, which is occasionally an incorrect parity value.  The assertion appears to work most of the time, but sometimes reports an error even though the values printed out in the error message indicate that the data and parity values are correct.  In the following simulation output, the first assertion failure is a real failure, but the second error seems to be incorrect — the value of parity is the right value for the value of data.

Simulation Output

# At 15: Requesting data
# ** Error: PARITY ERROR at 15 ns: data = 00, even parity = 1 (expected 0)
# ** Error: PARITY ERROR at 25 ns: data = 01, even parity = 1 (expected 1)
# At 45: Requesting data
# At 75: Requesting data


pcheck             P    F    F    P    P    P    P    P

         +----+    +----+    +----+    +----+    +----+
clk      |    |    |    |    |    |    |    |    |    |
     ----+    +----+    +----+    +----+    +----+    +----

     +        +--------------------------------------------
RSTn |        |

data    00 (hex)             | 01 (hex)          | 02 (hex)

parity        |

Why did the assertion show a second failure when the printed values are correct at that time?

See the answer