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Verilog/SystemVerilog for Design and Synthesis

April 25-29, 2016, 2016

5-days, $2,000 USD per person

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SystemVerilog Object Oriented Verification

May 9-13, 2016

5-days, $2,000 USD per person

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Mastering SystemVerilog UVM

May 23-26, 2016

4-days, $1,500 USD per person

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SystemVerilog Assertions for Design Engineers and Verification Engineers

(Next online date TBD)

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Sutherland HDL provides expert Verilog and SystemVerilog training services that help engineers become true Verilog and SystemVerilog wizards!

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